1. Field of the Invention
The subject matter disclosed herein generally relates to the manufacturing of integrated circuits, and, more particularly, to methods of forming a semiconductor structure wherein dopant profiles are created adjacent a feature formed on a substrate.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, such as transistors, capacitors and resistors. These elements are connected internally to form complex circuits, such as memory devices, logic devices and microprocessors. An improvement in the performance of integrated circuits requires a reduction of feature sizes. In addition to an increase in the speed of operation due to reduced signal propagation delays, reduced feature sizes allow increasing the number of functional elements in the circuit in order to extend its functionality.
FIG. 1b shows a schematic cross-sectional view of a field effect transistor 100 according to the state of the art. A substrate 101 comprises an active region 102. Shallow trench isolations 103, 104 isolate the active region 102 from neighboring circuit elements. A gate electrode 106 is formed over the substrate 101 and isolated from the substrate 101 by a gate insulation layer 105. The gate electrode 106 is flanked by sidewall spacers 117, 118.
Additionally, the field effect transistor 100 comprises an extended source region 109, an extended drain region 110, a source region 112 and a drain region 113. A portion of the extended source region 109, which is denoted as “source extension,” and a portion of the extended drain region 110, denoted as “drain extension,” extend below the sidewall spacers 117, 118 and are adjacent the gate electrode 106.
A method of forming the field effect transistor 100 is described with reference to FIGS. 1a and 1b. FIG. 1a shows a schematic cross-sectional view of the field effect transistor 100 in a first stage of the manufacturing process. First, the trench isolations 103, 104 and the active region 102 may be formed in the substrate 101. Then, the gate insulation layer 105 and the gate electrode 116 may be formed over the substrate 102. These structures may be formed using advanced techniques of ion implantation, deposition, oxidation and photolithography. In particular, the gate electrode 106 may be formed by photolithographically patterning a layer of material deposited over the substrate 101 and the gate insulation layer 105. Photolithography, which is well known to persons skilled in the art, comprises depositing a photoresist layer over the substrate 101 and exposing the photoresist layer.
After the formation of the gate electrode 106, the extended source region 109 and the extended drain region 110 may be formed by implanting ions of a dopant material into the substrate 101 adjacent the gate electrode 106. Parts of the substrate 101 outside the field effect transistor 100 which are not to be doped are covered by a layer of photoresist (not shown) which is configured to absorb ions.
After the formation of the extended source region 109 and the extended drain region 110, the sidewall spacers 117, 118 may be formed. To this end, a layer 111 of a spacer material may be conformally deposited over the substrate 101, e.g., by means of chemical vapor deposition (CVD). The spacer material may comprise silicon dioxide and/or silicon nitride. In conformal deposition, a local thickness of the deposited layer is substantially independent of a local slope of the surface on which it is deposited. In particular, the layer 111 has a substantially equal thickness on horizontal surfaces, such as the surface of the substrate 101 and the top surface of the gate electrode 106, and on vertical surfaces, such as the side surfaces of the gate electrode 106.
FIG. 1b shows a schematic cross-sectional view of the field effect transistor 100 in a later stage of the manufacturing process. The layer of spacer material 111 is etched anisotropically. In anisotropic etching, an etch rate in a vertical direction is greater than an etch rate in a horizontal direction. Therefore, portions of the layer of spacer material 111 whose surface is substantially horizontal, such as portions of the layer 111 on the top surface of the gate electrode 106 or on the surface of the substrate 101, are removed more quickly than inclined portions of the layer 111. In particular, portions of the layer 111 whose surface is substantially horizontal are removed more quickly than portions of the layer 111 whose surface is substantially vertical, such as portions of the layer 111 on the side surfaces of the gate electrode 106.
The etching of the layer 111 of the spacer material is stopped upon removal of the portions of the layer 111 having a horizontal surface. Due to the slower removal of portions of the layer 111 having a vertical surface, residues of these portions remain on the substrate and form the sidewall spacers 117, 118 adjacent the gate electrode 106. In some examples of methods of forming a field effect transistor according to the state of the art, the sidewall spacers 117, 118 may be part of one contiguous sidewall spacer structure running around the gate electrode 106.
Following the formation of the sidewall spacers 117, 118, the source region 112 and the drain region 113 may be formed by implantation of ions of a dopant material. The sidewall spacers 117, 118 absorb ions impinging on the sidewall spacers 117, 118. Therefore, the source region 112 and the drain region 113 may be provided at a greater distance to the gate electrode 106 than the extended source region 109 and the extended drain region 110. This allows the formation of a graded dopant profile, wherein the dopant profile below the sidewall spacers 117, 118 in the vicinity of the gate electrode 106 is relatively shallow and becomes deeper in the source region 112 and the drain region 113 which are provided at a greater distance to the gate electrode. As persons skilled in the art know, this may help to reduce short channel effects and, hence, may help to improve the performance of the field effect transistor 100 compared to a transistor wherein the source region 112 and the drain region 113 extend to the gate electrode 106.
In other examples of methods of manufacturing a field effect transistor according to the state of the art, further sidewall spacers may be formed adjacent the sidewall spacers 117, 118, and further implantations of dopant ions may be performed to create more sophisticated dopant profiles.
Finally, an annealing may be performed to activate dopants in the active region 102, the extended source region 109, the extended drain region 110, the source region 112 and the drain region 113.
A problem of the prior art method of forming a field effect transistor is that, in each of the processes employed in the formation of the sidewall spacers 117, 118, inhomogeneities may occur across the surface of the substrate 101, as well as between the processing of different substrates. Therefore, there may be a variation between dopant profiles in field effect transistors formed in different portions of the substrate 101, and between dopant profiles of field effect transistors formed on different substrates. Different dopant profiles, however, may entail different properties of the individual field effect transistors. This, in turn, may adversely affect the reproducibility of the method of manufacturing a field effect transistor according to the state of the art.
A further problem of the prior art method of forming a field effect transistor is that a loss of silicon in the substrate 101, as well as a loss of material of the shallow trench isolations 103, 104, may occur during the removal of the sidewall spacers 117, 118. This may also lead to a loss of dopants in regions in the vicinity of the gate electrode 106.
Yet another problem of the method of forming a field effect transistor according to the state of the art is that the sidewall spacers 117, 118 occupy an amount of space in the vicinity of the gate electrode 106. As the size of the field effect transistor 100 is reduced, it may be desirable to use this amount of space for different purposes, for example for forming electrical connections to the field effect transistor 100, or it may be desirable to provide a stress-creating layer in the vicinity of the gate electrode 106. As persons skilled in the art know, stress-creating layers may be employed to provide a compressive or tensile stress in a channel region of the field effect transistor 100 below the gate electrode 106, which may improve the mobility of electrodes and/or holes in the channel regions.
Therefore, it has been proposed to remove the sidewall spacers 117, 118 after the formation of the source region 112 and the drain region 113. This may be done by means of an etching process adapted to selectively remove the spacer material. The removal of the sidewall spacers 117, 118, however, may require further processing steps, which may increase the complexity of the formation of the field effect transistor 100. Moreover, the field effect transistor 100 may be damaged during the etching process.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.